Jetson Customize Pcie

Organization

NVIDIA-AI-IOT

jetson-customize-pcie

Per-controller PCIe enable / disable / lanes / link-speed for a Jetson Thor or Orin custom carrier via ODMDATA + kernel-DT overlay. Do NOT use for UPHY lane allocation or endpoint-mode bring-up.

Overview

Publisher	NVIDIA-AI-IOT
Repository	`jetson-bsp-skills`
Skill name	`jetson-customize-pcie`
Stars	73
Forks	13
Bundled files	6
License	Apache-2.0
Links	Skill source Repository

Markdown instructions
A SKILL.md file the model loads on demand, so it only costs tokens when a request actually matches.
Works with any LLM
AI skills are plain Markdown, not provider-specific code, so this works with GPT, Claude, Gemini, Grok, or a local model.
6 bundled files
Scripts, templates, and references the model can read while it works. Files are read-only and never executed.
Open source
Published by NVIDIA-AI-IOT on GitHub. Read the source before you install it.

Installation

Install the Jetson Customize Pcie AI skill in TypingMind to use it with any LLM, or drop it into another agent that reads SKILL.md.

Install in TypingMind

TypingMind installs a skill straight from its GitHub folder — it reads SKILL.md, bundles the resource files, and stores the result locally.

Open the app and go to Plugins → Skills.
Choose "Install from GitHub".
Paste the skill folder URL below and confirm.
https://github.com/NVIDIA-AI-IOT/jetson-bsp-skills/tree/main/skills/jetson-customize-pcie
Enable the skill in any chat where you want it available.

Store

Installed

Skills

Add skills

Import one or more skills from a public GitHub folder or a local .skill or .zip archive, or SKILL.md file.

From GitHub URLFrom .skill, .zip, or SKILL.md

GitHub repo or folder

https://github.com/NVIDIA-AI-IOT/jetson-bsp-skills/tree/main/skills/jetson-customize-pcie

Points to a single skill folder, or any folder that contains multiple skills. Public repos only.

CancelContinue

Plugins → Skills → Add skill → From GitHub URL, then paste the folder URL and press Continue.

Install in another agent

Any agent that reads the Agent Skills format can use this skill — copy the folder into that agent's skills directory.

Claude Code — .claude/skills

git clone --depth 1 https://github.com/NVIDIA-AI-IOT/jetson-bsp-skills.git /tmp/jetson-bsp-skills
mkdir -p .claude/skills
cp -r /tmp/jetson-bsp-skills/skills/jetson-customize-pcie .claude/skills/jetson-customize-pcie

Restart Claude Code after copying so it picks up the new skill.

Use it in TypingMind

Enable Jetson Customize Pcie in any TypingMind chat and the model takes it from there. Its name and description sit in the system prompt, and the moment a request matches, the model loads the full instructions itself — you never invoke it by hand, and it costs no tokens until it is actually used.

The model loads Jetson Customize Pcie on its own as soon as a request matches it.

Works with any AI model

AI skills are plain Markdown instructions rather than provider-specific code, so Jetson Customize Pcie is not tied to the model it was written for. Install it once in TypingMind and use it with GPT-5, Claude, Gemini, Grok, DeepSeek, Mistral, Llama, or a local model you run yourself — all on your own API keys.

Loaded only when it is needed
The system prompt carries just the name and description. The instructions are fetched on the first matching request, so an idle skill costs nothing.
Switch models mid-chat
Because the skill is instructions rather than code, changing model does not break it — the next model reads the same SKILL.md.

Skill instructions

This is the SKILL.md content the model loads. Read it before installing — a skill is instructions your model will follow.

Customize PCIe (per-controller status / lanes / speed)

Overview

PCIe on Tegra264 (Thor, pcie@C0..C5) and Tegra234 (Orin, pcie@C0..C10) is split across multiple controllers that share the UPHY lane pool with USB3 / MGBE / UFS. Each controller's runtime behavior is determined by two surfaces, both required:

Surface	Target	Authoritative for
ODMDATA `pcie@N_status=…` (+ `pcie@N_max-link-speed`, `pcie@N_pcie-mode`, `pcie@N_clk-scheme`, `pcie-cN-endpoint-enable`)	`/pcie/pcie@N` in BPMP DTB	UPHY lane power, refclk gating, controller-side power rails
Kernel-DT overlay on `&pcieN`	`/bus@0/pcie@<addr>` in kernel DTB	Kernel probe, lane width, link speed, RC/EP mode

Skipping the kernel overlay on a disable lets the kernel probe a powered-down PHY (link timeouts in dmesg). Skipping the ODMDATA token on a disable leaves BPMP holding the PHY hot.

Agentic, not table-driven — no controller table, no questions.json. Every controller, lane width, schematic-routed receptacle, and authoritative DT node address is discovered at runtime from the docs + DTB + carrier pinmap.

The output is a kernel-DT overlay commit only. Per-controller fragment@N blocks are appended to the composite custom overlay .dts per ../../references/bsp-customization-kernel-dtb.md and committed to the bsp_sources/ hardware repo. /jetson-build-source compiles the composite to .dtbo and owns its Makefile + flash-conf registration.

This skill MUST NOT edit ODMDATA="...". All ODMDATA tokens (pcie@N_status=…, pcie@N_max-link-speed, pcie@N_pcie-mode, pcie@N_clk-scheme, pcie-cN-endpoint-enable, plus the uphyX-config-N surface tokens and UPHY_CONFIG="" clear) are emitted by /jetson-customize-uphy in a single atomic commit on the carrier flash-conf fork. The allocation table this skill consumes from the UPHY sidecar already tells the operator which controllers are okay / disabled / per-lane sized; this skill only translates that table into kernel-DT overlay fragments and verifies that the overlay agrees with the ODMDATA already committed by customize-uphy (consistency check in Step 8 — disagreement is reported, not silently fixed).

When to invoke

The user says "configure PCIe", "enable PCIe controller", "set PCIe num-lanes", "change PCIe link speed", or asks to flip a pcie@N_status token.
A specific PCIe slot or M.2 receptacle doesn't enumerate after flash, OR the link trains at the wrong width / speed.
jetson-customize-uphy ran and re-allocated lanes across PCIe controllers (e.g. switched from uphy0-config-7 to uphy0-config-6 enabling PCIe C3); the per-controller side now needs to be brought up.
jetson-customize-mgbe reports the QSFP path is wired but the kernel doesn't probe its PCIe-side companion (rare; XFI configurations).

Prerequisites:

Active profile with reference_devkit: + custom_carrier: blocks.
<source.root_path>/Linux_for_Tegra/.git exists (/jetson-init-source).
/jetson-derive-carrier has run — carrier flash-conf fork is in the overlay tracker.
/jetson-customize-uphy has run — its JSON sidecar at <workspace>/target-platform/<profile-stem>.jetson-customize-uphy.json drives the per-controller enable decision.
Source-of-truth docs registered or supplied at prompt: Adaptation Guide, Module Design Guide, SoC TRM.
When custom_carrier: is present, both documents.custom_carrier_schematic AND documents.custom_carrier_pinmux_xls are REQUIRED. Refuse the run if either is missing — routing on a custom carrier cannot be guessed. Reference-devkit-only profiles skip this check.
dtc on PATH.

Procedure (summary)

Full step-by-step walkthrough lives in references/procedure.md. High-level flow:

Resolve active target + open source-of-truth documents (incl. <carrier-pinmap>, <ref-dtb>, <uphy-state>). Refuse if <uphy-state> is missing.
Diff PCIe topology — devkit vs custom carrier — by decompiling <ref-dtb> and grepping the schematic for PEX<N>_* net labels.
AskUserQuestion (multiSelect) — which controllers to customize.
Per-controller verification: pinmap + schematic + pin_verifier.py for PE<N>_CLKREQ_L, PE<N>_RST_L, optional PE<N>_WAKE_L.
Auto-derive per-controller plan (enable from <uphy-state>, lanes / speed from Adaptation Guide, mode hard-pinned to "rc") → mandatory confirm-or-customize gate.
Append per-controller fragment@N blocks (marker /* custom-bsp: pcie:pcie@<addr> */) to the composite custom overlay .dts in bsp_sources/. Pre-flight dtc + fdtoverlay. Commit via the workflow's preview gate. Do not edit ODMDATA — /jetson-customize-uphy already emitted pcie@N_status=…, pcie@N_max-link-speed, pcie@N_pcie-mode, pcie@N_clk-scheme, and pcie-cN-endpoint-enable in its single atomic ODMDATA commit. This skill only translates the per-controller plan into kernel-DT overlay fragments.
(Step folded into Step 6 — overlay-only emission.)
Cross-check ODMDATA vs overlay consistency. On a contradictory row, stop and ask the user how to recover the two commits. Never run git reset --hard autonomously.
Write run-state JSON sidecar at <workspace>/target-platform/<profile-stem>.jetson-customize-pcie.json
- summary, then drive the downstream next-step chain via sequential AskUserQuestion prompts per references/procedure.md Step 9. Never substitute a printed "Next step: …" line for the prompts.

Limitations

Mode hard-pinned to RC. Endpoint mode is only emitted when the operator passes mode_override="ep" in Step 5c.
enable is derived, not asked. UPHY-allocated controllers are mandatorily okay; non-allocated are mandatorily disabled.
No upstream BSP edits. Output lands in Linux_for_Tegra/ + bsp_sources/ only.
Pre-flight overlay merge is a sanity check, not the production build. /jetson-build-source is authoritative.
Flash-conf overlay registration is out of scope. Owned by /jetson-build-source Step 5.0a.

Troubleshooting

<uphy-state> missing → run /jetson-customize-uphy first.
Slot doesn't enumerate after flash → check dmesg | grep pcie; re-verify ODMDATA pcie@<N>_status=okay and the overlay fragment agree (Step 8 table in references/procedure.md).
Link trains at wrong width → confirm UPHY config in <uphy-state> allocates the expected lane count; the kernel fragment's num-lanes must match.
compatible mismatch → fix the composite root, not the fragment. UEFI plugin-manager silently skips on mismatch.
Contradictory ODMDATA-vs-overlay row → ask the user; do not auto-git reset --hard. See gotchas.
Common pitfalls — see references/gotchas.md (RC pinning, node- address sourcing, stock-disabled controllers, intra-file handoff with jetson-customize-uphy).

References

references/procedure.md — full nine- step procedure (topology diff, plan derivation, overlay append, ODMDATA cross-check, sidecar).
references/gotchas.md — failure modes
- invariants (RC pinning, address sourcing, BPMP handoff).
../../scripts/pin_verifier.py — shared HSIO pin verifier (Step 4).
../../references/platform_template.yaml — documents: block consumed by Step 1.
../../context/bsp-customization-workflow.md — overlay edit protocol + commit message preview gate.
../../references/bsp-customization-kernel-dtb.md — composite overlay filename / skeleton / append protocol.
../jetson-customize-uphy/SKILL.md — sibling skill that owns UPHY lane allocation; its sidecar drives the per-controller enable decision.
../jetson-customize-pinmux/SKILL.md — sibling skill invoked by Step 4 (with operator confirmation) to fix HSIO pin SFIO mismatches.
../jetson-customize-mgbe/SKILL.md — sibling for MGBE controllers; shares the two-surface (ODMDATA
- overlay) pattern.
../jetson-derive-carrier/SKILL.md — must run first; produces the carrier flash-conf fork edited in Step 6.
../jetson-init-source/SKILL.md — produces the overlay tracker + bsp_sources repo this skill commits into.

Bundled files

The model reads these on demand while the skill is loaded. They are exposed as readable files and are never executed.

Frequently asked questions

What does the Jetson Customize Pcie AI skill do?

Per-controller PCIe enable / disable / lanes / link-speed for a Jetson Thor or Orin custom carrier via ODMDATA + kernel-DT overlay. Do NOT use for UPHY lane allocation or endpoint-mode bring-up.

Why use Jetson Customize Pcie on TypingMind?

Because you install it once and use it with any model. Jetson Customize Pcie is plain Markdown rather than provider-specific code, so the same skill runs on GPT-5, Claude, Gemini, Grok, or a local model — and you can switch model mid-chat without it breaking. TypingMind runs on your own API keys, so you pay providers directly instead of a per-seat subscription, and your skills and chats stay in your own storage.

How do I install Jetson Customize Pcie in TypingMind?

Open Plugins → Skills → Install from GitHub in TypingMind and paste https://github.com/NVIDIA-AI-IOT/jetson-bsp-skills/tree/main/skills/jetson-customize-pcie. TypingMind reads its SKILL.md and bundles its files and installs it as a skill you can enable per chat.

Which AI models can use Jetson Customize Pcie?

Any model you connect in TypingMind. AI skills are plain Markdown instructions rather than provider-specific code, so GPT, Claude, Gemini, Grok, and local models can all load this skill when a request matches it.

How many AI models can I use with Jetson Customize Pcie?

As many as you like. As long as a model supports skills, you can use Jetson Customize Pcie with it — GPT, Claude, Gemini, Grok, DeepSeek, Mistral, Llama and more — all on TypingMind with your own API keys.

Is the Jetson Customize Pcie AI skill free?

Yes. It is published on GitHub by NVIDIA-AI-IOT under the Apache-2.0 license. You only pay your own AI provider for the tokens you use.

What are AI skills?

An AI skill is a reusable instruction bundle that teaches an AI model how to do one specific task. It follows the open Agent Skills format: a SKILL.md file with a name and description, plus any scripts, templates or reference files the model may need. The model reads the instructions only when your request matches the skill, so an installed skill costs nothing until it is used.

How are AI skills different from plugins or MCP servers?

A plugin or MCP server gives a model new tools to call — code that runs somewhere and returns a result. An AI skill gives the model knowledge and process instead: how to approach a task, which steps to follow, what good output looks like. Skills are plain Markdown, so they need no server, no API key and no runtime, and they work with any model.

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Overview

Installation

Install in TypingMind

Install in another agent

Use it in TypingMind

Works with any AI model

Skill instructions

Customize PCIe (per-controller status / lanes / speed)

Overview

When to invoke

Procedure (summary)

Limitations

Troubleshooting

References

Bundled files

Frequently asked questions

Related AI Skills

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